1. Field of the Invention
The present invention relates to a boost circuit, and more particularly, to a boost circuit whose output voltage is equal to the maximum rated voltage.
2. Description of the Related Art
The boost circuit has been applied in the EEPROM (Electrically erasable programmable read only memory) for a couple of years. FIG. 1 schematically shows a conventional Dickson boost circuit. As shown in FIG. 1, the conventional Dickson boost circuit comprises an input stage 10, a plurality of booster stages (12, 14, 16, 18, and 20), and an output stage 22. Wherein, the input stage 10 is mainly composed of an NMOS transistor 24. A drain and a gate of the NMOS transistor 24 are connected and jointly receive an input voltage Vin, and a source is electrically coupled to the first booster stage 12. Each booster stage comprises an NMOS transistor and a coupling capacitor, and the booster stage 12 is exemplified herein for describing the connection. A drain and a gate of the NMOS transistor 26 are jointly connected to a first terminal of the coupling capacitor 28, and a source is serially connected to a drain of a next boost stage 14. A second terminal of the coupling capacitor 28 receives a first clock signal Vphi1. In addition, two different clocks signal are provided as shown in the diagram. The first clock signal Vphi1 is provided to the coupling capacitor disposed in the odd number booster stages (e.g. the booster stages 12, 16, and 20), and the second clock signal Vphi2 is provided to the coupling capacitor disposed in the even number booster stages (e.g. the booster stages 14 and 18). As shown in FIG. 2, the first clock signal Vphi1 is not overlapped with the second clock signal Vphi2, and they are the complementary signals with a voltage of VDD. In addition, the output stage is composed of a greater output capacitor Cout.
During the operation, when the first clock signal Vphi1 rises to a high voltage, the drain voltage of the NMOS transistor in the odd number booster stages (e.g. the booster stages 12, 16, and 20) is pulled up due to the coupling effect generated by the coupling capacitor, and this high voltage is then transmitted to the even number booster stages. Then, when the second clock signal Vphi2 rises to a high voltage, the drain voltage of the NMOS transistor in the even number booster stages (e.g. the booster stages 14 and 18) is pulled up due to the coupling effect generated by the coupling capacitor. With such method, the voltage rises to a desired high voltage value.
However, since there is a potential difference between the gate and the source of each transistor, if it is desired to obtain a desired output voltage from the source of the transistor in each booster stage, a voltage higher than the output voltage of the source should be provided to the drain of each transistor. Using the booster stage 20 as an example, if it is desired to output a desired output voltage Vout from the source of the transistor 32, the input voltage Vina provided to the drain of the transistor 32 must be higher than the output voltage Vout, thus the voltage difference V1 between the gate and the source of the transistor 32 can be overcome. In addition, since the drain voltage of each transistor must be higher than the source voltage, the transistor is easily damaged by the drain voltage, which causes problems such as the current leakage or circuit latch-up.